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datasheet ax5031 v e rsi o n 1. 3
version 1.3 datasheet ax5031 2 document type datasheet document status document version version 1.3 product ax5031
tabl e of con t en ts 3 table of co ntents 1. overvi ew ............................................................................................................................... ..... 5 1. 1. fea t ur es ............................................................................................................................... ............ 5 1. 2. appl icat ions ............................................................................................................................... ..... 5 2. block diagr am ........................................................................................................................... 6 3. pin function descriptions .......................................................................................................... 7 3. 1. pin lis t ............................................................................................................................... ................ 7 3. 2. pinout dra w ing ............................................................................................................................... 8 4. specifi catio n s ............................................................................................................................ 9 4. 1. a b solu te ma ximu m ra t i n g s .......................................................................................................... 9 4. 2. dc chara c terist ics ....................................................................................................................... 1 0 supplies ............................................................................................................................... ........... 1 0 logic ............................................................................................................................... ................ 1 1 4. 3. ac charac terist ics ....................................................................................................................... 1 2 cryst a l oscillat o r ........................................................................................................................... 1 2 rf fre q u e ncy g e ne rat i on su bsyst e m ( s ynt h e s ize r ) ................................................................ 1 3 transmi tte r ............................................................................................................................... ....... 1 4 spi timing ............................................................................................................................... ......... 1 5 5. circuit descr i ption ................................................................................................................... 16 5. 1. v o ltag e r e g u la to r ....................................................................................................................... 1 7 5. 2. cryst a l oscillat o r ........................................................................................................................... 1 7 5. 3. sy s c lk o u tput .............................................................................................................................. 1 8 5. 4. powe r-on-reset ( p or) .................................................................................................................. 1 8 5. 5. rf frequency genera t i o n subsystem ....................................................................................... 1 8 vc o ............................................................................................................................... ................. 1 9 vc o a u t o - r a n g i n g ...................................................................................................................... 1 9 loop filter and charge pump .................................................................................................... 1 9 versi o n 1. 3 datasheet a x 5031
tabl e of con t en ts 4 registers ............................................................................................................................... .......... 1 9 5. 6. rf ou tpu t s t age ( a ntp/a n tn) ................................................................................................... 2 0 5. 7. encod e r ............................................................................................................................... .......... 2 0 5. 8. framing and fi f o ......................................................................................................................... 2 1 hdlc mode ............................................................................................................................... .... 2 2 ra w mode ............................................................................................................................... ...... 2 2 80 2. 15. 4 ( z igbe e) ........................................................................................................................... 2 2 5. 9. modu l a t o r ............................................................................................................................... ....... 2 3 5. 10. p w rm ode regi s t er ................................................................................................................ 2 4 5. 11. serial peripheral in terfac e ( s pi ) ............................................................................................ 2 5 spi timing ............................................................................................................................... ......... 2 5 6. register ban k descriptio n ....................................................................................................... 26 6. 1. cont ro l regi ster map ................................................................................................................... 2 7 7. application information .......................................................................................................... 30 7. 1. typical applicat ion diag ram ..................................................................................................... 3 0 7. 2. ant e nna interface circuit r y ........................................................................................................ 3 1 single-ended anten n a in terface ............................................................................................... 3 1 7. 3. v o ltag e r e g u la to r ....................................................................................................................... 3 1 8. qfn2 0 pac k age inf o r m a t ion .................................................................................................. 32 8. 1. packag e o u tli n e q f n 2 0 ............................................................................................................. 3 2 8. 2. qfn sol d e r ing profil e ................................................................................................................... 3 3 8. 3. qfn re co mmende d pad layout .............................................................................................. 3 4 8. 4. assemb ly process ......................................................................................................................... 3 4 s t e n ci l d e si g n & so ld er p a s t e a p p l i c a t i o n ............................................................................... 3 4 9. life support applications ........................................................................................................ 36 10 . contact in formation ................................................................................................................ 37 versi o n 1. 3 datasheet a x 5031
tabl e of con t en ts 5 1. overv i ew 1. 1 . features ? advan ced multi-chann e l single chip uhf tra n smitter ? configurable for usage in 400- 470 mhz and 800-940 m h z srd bands ? -5 dbm to +15 dbm progr a mmable output ? 17 m a @ 0 d b m, 8 6 8 mh z ? 3 0 ma @ 10 dbm, 86 8 mh z ? 4 6 ma @ 14 .5 dbm, 86 8 mh z ? wide variety of shaped modulations supported (ask, psk, oqpsk, m s k, fsk, gfsk, 4-fsk) ? data rates fr om 0.1 to 200 kbps (fsk, m s k, g f sk; 4-f s k) a n d to 2000 kbps (ask, psk) ? ultra fast sett ling rf fr equency synthesizer for low - power consumptio n ? 80 2. 1 5 . 4 c o m patible ? rf carrier fre q uency and fsk deviation programmable in 1 hz steps ? fully integrat ed rf freque ncy synthesizer with vc o au to-ranging and band-width boost modes for fast locking ? few extern al comp o nents ? on chip c o mmunicatio n controller and flexible digital modu lator ? channel hopping 2000 hops/s ? crystal oscill ator with programmable transcon ductance and programmable internal tuning capacitors for low cost crystals ? spi micro- co ntroller interface ? qfn20 pa ckage ? supply volta g e r a nge 2. 2 v - 3. 6v ? internal po wer-on-reset ? 32 byte data fifo ? programma ble cycli c r e dundancy check (crc -ccitt, c r c - 16, crc - 32) ? optional spectral shaping using a self synchro n izing shift r e gister ? brown-out d e tection ? differentia l a n tenna pins ? dual frequency registers ? internally generated cod ing for forw ard viterbi error correction ? soft ware c o m patible to ax5051 1. 2. a ppli c a t ions 40 0- 4 7 0 m h z and 8 00- 94 0 m h z d a t a t r ans m ission in t h e s h o r t rang e d e v i c e s (s r d ) b a n d . ? te lemetric appl icat io ns, se nsor readout ? toys ? w i reless a u d i o ? w i reless n e tworks ? w i reless u s b ? access co ntrol ? remo te k e y l ess en try ? ari b co mpat ible ? poin t i ng devices and k e y b oards ? act i v e rfid ? rf i d b a se st at ion t r ans m it t e r ? 43 3/ 86 8/ 91 5 m h z srd band sys t ems versi o n 1. 3 datasheet a x 5031
block diagra m 6 2. block diagram a x5031 ant p crys t a l osci ll at o r ty p . 16 m h z f ou t rf frequency genera t i o n subsy s t e m f xta l c o m m u n i c a t io n c o nt r o lle r & seria l i n t e rface divid e r pa enco de r fr a m i n g fif o mo d u la t o r syscl k cl k 16n ir q chip configura t i o n se l cl k mi so mosi v re g vdd_i o vol t age reg u l a t o r por f o rward err o r correcti o n ant n cl k 16p figure 1 fun c tio nal block diagram of the ax503 1 versi o n 1. 3 datasheet a x 5031
pin fun c t i on descrip t ion s 7 3. pin fu nct i o n de sc ri pt ion s 3. 1 . pin list symbol pin ( s ) type description vd d 1 p pow e r suppl y, must b e suppl ie d w i t h reg u l a t e d v o l t age v r eg an t p 2 a a n ten n a o u tp u t an t n 3 a a n ten n a o u tp u t vd d 4 p pow e r suppl y, must b e suppl ie d w i t h reg u l a t e d v o l t age v r eg nc 5 n nc 6 n sysc lk 7 i/ o defaul t func t i o n al it y: cryst a l osci ll at or ( o r di v i ded ) cl ock output can be pr og ra mme d to be us e d as a ge ne ra l purpose i / o pi n sel 8 i serial periphera l int e rface s e l e ct clk 9 i serial periphera l int e rfa c e cl oc k mi so 10 o serial periphera l int e rfa c e da ta ou t p u t nc 11 n mosi 12 i serial periphera l int e rfa c e da ta input nc 13 n irq 14 i/ o defaul t func t i o n al it y: i n terrup t can be pr og ra mme d to be us e d as a ge ne ra l purpose i / o pi n v dd_i o 15 p u n reg u l a te d pow e r suppl y nc 16 n vr e g 17 p r e g u la t e d out p u t v o lt a g e vdd pins mus t be connec t e d t o this supply v o l t ag e a 1f l o w esr c a pacitor t o g n d must b e con n ec ted to t h is pin vd d 18 p pow e r suppl y, must b e suppl ie d w i t h reg u l a t e d v o l t age v r eg cl k16p 19 a c r y s ta l o s c i l l a t o r i n p u t/ o u tp u t cl k16n 20 a c r y s ta l o s c i l l a t o r i n p u t/ o u tp u t gnd cen t re pad p ground on c e n t r e pad of q f n a = anal og signal i / o = d i gi ta l i n p u t/ o u tp u t s i g n a l i = dig i t a l input signal n = n o t to b e c o n n e c t ed o = d i gi ta l o u tp u t s i g n a l p = po w e r or grou n d all dig i t a l inputs are schmi tt t r ig ge r inpu t s , dig i t a l inpu t an d ou t p u t l e v e l s are lvcmo s /lvtt l c o mpa t ible an d 5 v to l e r a n t . versi o n 1. 3 datasheet a x 5031
pin fun c t i on descrip t ion s 8 3. 2 . pinout drawing clk16p clk16 n vreg vdd nc 19 16 18 17 20 vd d 12 13 14 15 11 vd d _ i o 1 irq an tp 2 ax5031 nc an tn 3 mos i vd d 4 nc nc 5 6 7 8 10 9 mi s o sysclk clk sel nc figure 2: pinout drawing ( t op v i ew) versi o n 1. 3 datasheet a x 5031
spe c ificat ions datasheet a x 5031 9 4. specific a tions 4. 1. a b solu te maximu m ra ting s st re sses abov e t h ose l i st e d u n d e r absolu te maximu m r a t i ngs may cau s e p e r m an en t damage to th e de v i c e . this is a st re ss rat i ng onl y ; fu nct i onal operat ion of the dev i ce at t h ese or any ot he r condit ions abo v e t h o s e l i ste d in t h e ope r at ional se ct io ns of t h is spe c ificat ion is no t impl ie d. expos u re t o abso lu te m a ximu m ra t i ng condi t io ns for e x te nde d pe riods may affe ct dev i c e r e l i a b il it y . symbol descr i pt ion condit ion min ma x unit v dd_i o s u p p l y v o l t ag e -0. 5 5. 5 v i d d s u p p l y curre nt 1 0 0 ma p to t t o t a l pow e r consumpt ion 800 m w i i1 dc curr en t in to any pin e x ce pt an t p , an t n - 1 0 1 0 ma i i2 d c c u r r en t i n t o p i n s a n t p , an t n - 1 0 0 1 0 0 ma i o out p u t c u rren t 40 ma i n p u t v o lt a g e an t p , an t n pins - 0 . 5 5. 5 v v ia i n p u t v o l t a g e d i gi ta l p i n s - 0 .5 5 . 5 v v es el e c t r os t a t i c ha ndl ing hbm -2000 2000 v t amb o p era t i n g tem p era t ur e -4 0 8 5 c t st g st ora g e te mp e r at ur e -65 150 c t j junct i on t e mp e r a t ur e 150 c versi o n 1. 3
spe c ificat ions 10 4.2 . dc ch ara c t e ri sti c s supplies symbol descr i pt ion condit ion min . typ. ma x. unit t am b ope r a t ional ambie n t te mpe r at ur e -40 27 85 c vdd_i o i / o and v o l t age regul a t o r sup p ly vo lt a g e 2 . 2 3. 0 3. 6 v p o we r - d o wn m o d e p w rmod e=0x00 1 . 7 v vreg int e rnall y re g u late d suppl y vo lt a g e all ot he r p o w e r mode s 2. 1 2. 5 2. 8 v i pdow n pow e r-dow n cu rre nt p w rmod e=0x00 0. 25 a 868 mhz, 14. 5 dbm 46 868 mhz, 13 dbm 41 868 mhz, 10 dbm 30 868 mhz, 13 dbm 41 868 mhz, 4 dbm 19 868 mhz, 0 dbm 17 433 mhz, 15 dbm 46 433 mhz, 13 dbm 40 433 mhz, 10 dbm 29 433 mhz, 4 dbm 18 i tx curren t co nsumpt ion tx 433 mhz, 0 dbm 17 ma versi o n 1. 3 datasheet a x 5031
spe c ificat ions 11 log i c symbol descr i pt ion condit ion min . typ. ma x. unit d i g i ta l i n p u ts v t+ s c h m it t t r ig g e r low t o h i g h t h re shol d point 1. 9 v v t- s c h m i t t tr i g g e r h i gh to l o w t h re shol d point 1. 2 v v il input v o l t age, low 0. 8 v v ih input v o l t age, hig h 2. 0 v i l input l e akag e curre nt -10 10 a digit a l output s i oh out p u t curr en t, high v oh = 2. 4 v 4 ma i ol out p u t curr en t, l o w v ol = 0. 4 v 4 ma i oz tri - s t a t e ou tp u t l e ak ag e cur r en t -1 0 1 0 a versi o n 1. 3 datasheet a x 5031
spe c ificat ions 12 4. 3. a c chara c ter i s t ic s cryst a l osci llat o r symbol descr i pt ion condit ion min . typ. ma x. unit f xta l cryst a l fre q ue ncy n o te 1 16 mhz x t a l oscg m = 0 0 0 0 1 x t a l oscg m = 0 0 0 1 2 x t a l oscg m =0010 defaul t 3 x t a l oscg m =0011 4 x t a l oscg m =0100 5 x t a l oscg m =0101 6 x t a l oscg m =0110 6. 5 x t a l oscg m =0111 7 x t a l oscg m =1000 7. 5 x t a l oscg m =1001 8 x t a l oscg m =1010 8. 5 x t a l oscg m =1011 9 x t a l oscg m =1100 9. 5 x t a l oscg m =1101 10 x t a l oscg m =1110 10. 5 gm os c transc ondu c t a n ce oscil l a t o r x t a l oscg m =1111 11 ms x t a l ca p = 0 0 0 000 defaul t 2 pf c osc programmabl e t u ning capacitors at pins cl k16n and cl k16p x t a l ca p = 1 1 1 111 33 pf c osc - l s b programmabl e t u ning capacitors , incr emen t per ls b of xt al c a p 0. 5 pf a osc osci ll at or ampl i t u d e a t pin cl k16p 0. 5 v ri n osc input dc impedanc e 10 k ? not e s 1. t o l e rances an d st ar t - up t i m e s depend on t he cry s t a l used. versi o n 1. 3 datasheet a x 5031
spe c ificat ions 13 r f fr e q uen c y ge ner a t i on s u bs ys t e m ( s yn t h esi z er) symbol descr i pt ion condit ion min . typ. ma x. unit f re f re fe r e nc e fr e q ue ncy 16 mhz f range_hi ba n d sel = 0 8 0 0 9 4 0 f range_lo w f r e q ue nc y r a ng e ba n d sel = 1 4 0 0 4 7 0 mhz f re so frequ e n c y resol u t i o n 1 hz bw 1 loop f i l t er c o nf i g ura t i o n : fl t= 0 1 char g e pump curre nt: p l lcpi=010 1 0 0 bw 2 loop f i l t er c o nf i g ura t i o n : fl t= 0 1 char g e pump curre nt: p l lcpi=001 5 0 bw 3 loop f i l t er c o nf i g ura t i o n : fl t= 1 1 char g e pump curre nt: p l lcpi=010 2 0 0 bw 4 sy nthesizer l o op band w i d t h loop f i l t er c o nf i g ura t i o n : fl t= 1 0 char g e pump curre nt: p l lcpi=010 5 0 0 khz t set 1 loop f i l t er c o nf i g ura t i o n : fl t= 0 1 char g e pump curre nt: p l lcpi=010 1 5 t set 2 loop f i l t er c o nf i g ura t i o n : fl t= 0 1 char g e pump curre nt: p l lcpi=001 3 0 t set 3 loop f i l t er c o nf i g ura t i o n : fl t= 1 1 char g e pump curre nt: p l lcpi=010 7 t set 4 sy nthesizer sett l i ng t i m e for 1mhz s t e p loop f i l t er c o nf i g ura t i o n : fl t= 1 0 char g e pump curre nt: p l lcpi=010 3 s t st a r t 1 loop f i l t er c o nf i g ura t i o n : fl t= 0 1 char g e pump curre nt: p l lcpi=010 2 5 t st a r t 2 loop f i l t er c o nf i g ura t i o n : fl t= 0 1 char g e pump curre nt: p l lcpi=001 5 0 t st a r t 3 loop f i l t er c o nf i g ura t i o n : fl t= 1 1 char g e pump curre nt: p l lcpi=010 1 2 t st a r t 4 synthe size r s t art-up t i m e if cry s t a l oscill at or and refer e n c e ar e r u nning loop f i l t er c o nf i g ura t i o n : fl t= 1 0 char g e pump curre nt: p l lcpi=010 5 s 868 mhz, 50 khz from carrie r -85 868 mhz, 100 khz from carri e r -90 868 mhz, 300 khz from carri e r -100 pn 868 1 868 mhz, 2 mh z from carrie r -110 433 mhz, 50 khz from carrie r -90 433 mhz, 100 khz from carri e r -95 433 mhz, 300 khz from carri e r -105 pn 433 1 sy nthesizer pha s e noise l o o p f i lt e r co n f ig u r at i o n: f l t = 01 char ge pump curren t : pl l c pi =010 433 mhz, 2 mh z from carrie r -115 dbc/h z 868 mhz, 50 khz from carrie r -80 868 mhz, 100 khz from carri e r -90 868 mhz, 300 khz from carri e r -105 pn 868 2 868 mhz, 2 mh z from carrie r -115 433 mhz, 50 khz from carrie r -90 433 mhz, 100 khz from carri e r -95 433 mhz, 300 khz from carri e r -110 pn 433 2 sy nthesizer pha s e noise l o o p f i lt e r co n f ig u r at i o n: f l t = 01 char ge pump curren t : pl l c pi =001 433 mhz, 2 mh z from carrie r -122 dbc/h z versi o n 1. 3 datasheet a x 5031
spe c ificat ions 14 trans m itte r symbol descr i pt ion condit ion min . typ. ma x. unit a s k & psk 0. 1 2000 sbr signal bit ra te f s k 0 . 1 2 0 0 kbps t x r n g = 0 0 0 0 - 4 5 t x r n g = 0 0 0 1 - 5 t x r n g = 0 0 1 0 0. 4 t x r n g = 0 0 1 1 4 t x r n g = 0 1 0 0 6. 2 t x r n g = 0 1 0 1 8 t x r n g = 0 1 1 0 9. 3 t x r n g = 0 1 1 1 10. 3 t x r n g = 1 0 0 0 11. 2 t x r n g = 1 0 0 1 11. 9 t x r n g = 1 0 1 0 12. 5 t x r n g = 1 0 1 1 1 3 t x r n g = 1 1 0 0 13. 5 t x r n g = 1 1 0 1 13. 8 t x r n g = 1 1 1 0 1 4 pt x 868 t r ansmi tte r po w e r @ 868 mh z t x r n g = 1 1 1 1 14. 5 dbm pt x 433 t r ansmi tte r po w e r @ 433 mh z t x r n g=1111 15. 5 dbm pt x 868- harm2 e m ission @ 2 nd harmonic -50 pt x 868- harm3 e m ission @ 3 rd h a rmonic no te 1 - 5 5 dbc not e s 1. addit i on al l o w - pass fi l t ering w a s app l ie d t o t he an t enna in t e rf ace, see sect i o n 7: a p p l icat i o n i n form at i o n. versi o n 1. 3 datasheet a x 5031
spe c ificat ions 15 spi t i ming symbol descr i pt ion condit ion min . typ. ma x. unit t ss se l fal ling e d ge t o cl k rising e d g e 10 ns t s h cl k fall ing e d ge t o se l rising edge 10 ns t ssd se l fal ling e d ge t o mi so dri v ing 0 10 ns t ssz se l rising edge t o mi so hig h -z 0 10 ns ts m o s i s e tu p ti m e 1 0 n s th mosi ho l d t i me 10 ns t c o cl k fall ing e d ge t o mi so out p ut 10 ns t c k cl k pe riod n o te 1 50 ns t c l c l k low d u r a t i on 4 0 n s tch clk high dura t i on 40 ns not e s 1. for sp i acce ss d u ring pow e r-d o w n m o d e t he period shoul d be re l a xed t o 10 0ns. for a figu r e showing the spi t i mi ng para me ter s se e s e c t i o n 5. 11: serial periph era l in terf ac e (s p i ) . versi o n 1. 3 datasheet a x 5031
circui t d e scr i pt ion 16 5 . ci rc ui t de sc ri pt io n the ax 503 1 is a t r u e singl e chip l o w-powe r cmos t r ansmi t te r primari l y for u s e in sr d bands. the o n -chip t r ansce i v e r consists of a full y in t e g r a t e d r f f r o n t- e n d w i th m o d u l a to r, a n d demod u la to r. base ban d data pro c essing is i m pl eme n t e d in an ad v a nce d and fl e x ible commu n icat ion co nt ro l l e r t h at e n abl e s u s e r frie ndl y commu n icat ion v i a t h e spi interface . a x 50 31 can be operated from a 2. 2 v t o 3. 6 v power s u pp l y o v er a te mp era t ure r a nge of -4 0 o c t o 85 o c , it consumes 11 - 45 ma for t r ansmit ting, depending on the out p ut power. the ax 50 3 1 fe at u r es make i t an ideal int e rface for int e grat i o n int o v a ri ou s batt e r y powe re d s r d s o l u ti o n s s u c h a s ti c k e t i n g o r a s tr a n s m i t t e r for t e le met r i c appl icat io ns e . g . in sensors. as primary appl icat ion, t h e t r ansmi t te r is int e nde d fo r u h f radio e q u i pme n t i n accordance wi th the e u rope an te le co mmu n icat ion st andard i n st i t ut e ( e tsi ) spe c ificat ion en 30 0 22 0 - 1 and the u s federal com m unica t ion s co m m ission ( f cc) standard cfr47, part 15. the use of a x 50 31 in accord anc e to f c c pa r 1 5 . 247, allo ws f o r i m pro v ed rang e i n the 91 5 m h z ba nd . a d d i t i ona lly a x 5 0 5 1 i s compa t i b l e wi th t h e lo w f r e q u e ncy s t an d a rd s of 802 . 15. 4 ( z igbee ) . the ax 503 1 recei v e s da ta v i a th e sp i por t in fra m es . this st andard ope r ation mode is call e d frame mode. pre and post a m bles as well as chec ksums can be g e nera ted auto ma t i ca lly. interrupt s cont rol the da ta flow b e tw ee n a con t r o ll er and the a x 50 31 . the ax 50 3 1 be hav e s as a spi slav e int e rface . configu r at ion of t h e a x 50 31 is also done v i a th e sp i in terf ace. a x 50 31 su p p or t s a n y d a t a ra te f r om 0. 1 kb ps t o 2 0 0 kb ps f o r fsk and m s k and f r om 0. 1 kb ps t o 2 000 kbps for ask and psk. to ac hiev e opt i mu m pe rformance for spe c ific dat a rat e s and modula t i on schemes severa l register sett i n gs t o configure t h e ax 503 1 are n e ce ssary , they ar e outl ine d in the foll owing , for de t a ils se e the ax 50 31 programming manual. spreading is possible on all da ta ra tes and mo dula t i o n sch e mes. the net tran sfer rate is red u c e d by a f a ct or of 15 i n thi s ca se. for zi gbee ei ther 60 0 or 300 k bps mod e s h a ve t o b e chosen. versi o n 1. 3 datasheet a x 5031
circui t d e scr i pt ion 17 5. 1. v o ltage r e gula t o r the ax 50 3 1 u s e s an on-chip v o lt ag e re gul a t o r t o cre a te a st able suppl y v o ltage for t h e i n te r n a l c i r c u i tr y a t p i n v r e g f r o m th e p r i m a r y s u p p l y v d d _ i o . a ll v d d pi n s o f th e d e vi c e m u s t be con n ec t e d t o v r eg. the an te nn a pi ns a n tp and a n tn mu s t b e dc bi ased t o v r eg. the i/ o l e ve l o f the d i g i tal pi ns i s v dd_io . the v o ltage regula t o r r e quires a 1 f low esr cap a cit o r a t pin v r eg. in powe r-down mod e t h e v o lt ag e regu l a tor t y picall y out p uts 1 . 7 v at v r e g , if it is powe re d-up it s o u tput rises t o t y pically 2. 5 v . at dev i ce po we r-u p t h e re g u l a t o r is in p o w e r - do w n mo de . the vo l t ag e regu la t o r m u s t b e pow e re d-u p be fo re t r ansmi t o p e r at ions can be ini t iated. this is handle d automat i cal l y whe n programming t h e dev i ce mo de s v i a the pwrmode reg i s t er . register vreg cont ains st at u s bi t s t h at can be re ad t o che c k if t h e re gul a t e d volt ag e is abo v e 1. 3 v or 2. 3 v , st i c ky versi o ns of t h e bi t s a r e pro v i d ed tha t c a n b e used t o d e t e c t low power events ( b rown-out d e tect io n). 5. 2 . cryst a l osci llat o r the o n - c hi p cry s t a l osc i lla t o r al low s t h e us e of an i n exp e nsi v e q u ar tz cry s t a l as th e rf g e n e r a ti o n s u b s y s t e m ? s ti m i n g r e f e r e n c e . a l t h ough a wider range of crystal frequencies can be hand l e d by t h e crystal oscill at or circu i t , it is re comme nd e d t o u s e 16 mhz as refe re nc e fre q ue ncy si nce this choi ce al l o ws all t h e t y pi cal srd band rf frequencies t o be g e nera t e d. the oscill at o r circu i t is e n able d by programming t h e pwrmode r e g i s t e r . a t p o w e r - u p i t i s n o t ena b l e d . to adjus t th e ci rcui t?s c h arac teri s t i c s t o th e q u a r tz cry s t a l be i n g us ed wi thou t u s i n g a ddi t i ona l ex terna l co mpon en ts, both the tran s c ond u c t anc e and th e tu ni ng capaci tanc e of t h e cry s t a l oscilla tor ca n be progra mmed. the t r a n sco n ductance is programmed v i a re gister bi t s xtaloscgm[3: 0] in regist er xtal osc . the i n tegra t ed program m ab le tu ni n g capaci t o r b a n k m a ke s it p o ss ib le t o con n e ct t h e oscilla tor directly t o pins clk16n and clk16p wi t h out the need for external capa ci t o r s . it is programmed using bi t s xtalcap[5: 0] in register xtal cap . versi o n 1. 3 datasheet a x 5031
circui t d e scr i pt ion 18 5. 3 . sy sclk output the s y scl k pin o u t p uts the refer e nce cloc k signal di v i ded by a pro g rammable inte ge r. div i sions fro m 1 t o 2048 are possi ble. for di v i d e r ra t i os > 1 the d u t y cy cle i s 50% . bi t s s y sc l k [3 :0 ] i n t h e pincfg1 regist er set the di v i der rat i o. the sy s c lk o u tput can be disabled. 5. 4. power - on-reset ( p or) a x 50 31 has an integra t ed power-on-reset block. no ex ter n al por circui t or signal is required. aft e r por t h e a x 50 31 c a n b e r e s e t b y s p i a c c e s s e s , t h i s i s a c h i e v e d b y t o g g l i n g t h e b i t r s t i n th e pwrmode regist er. a f ter por or rese t a ll r e gi s t ers are s e t t o th ei r d e f a ul t v a l u es. 5.5 . rf freq uen c y generati on subsystem the rf f r eq ue ncy gen e ra t i on s u b s y s te m consi s t s of a fu lly inte grated synt he sizer , which mult ipl i es t h e re fe re nce fre q ue ncy from t h e cryst a l oscill at or to get t h e desired rf frequency. the ad vanc ed archi t ec ture of t h e sy n t h e si z e r en abl e s f r eq u e ncy resol u t i o n s of 1 hz, as wel l a s fas t s e ttli n g times of 5 ? 5 0 s de pe nd ing on t h e set t i n gs ( s e e se ct io n 4 . 3 : ac charact e rist ics). f a st set t l in g t i me s me an fast st art - up , w h ich en abl e s l o w - p o we r s y st em des i gn . the f r eq u e n c y mus t b e programm e d t o the desi red carrier frequency. th e s y nt he s i ze r l oop b a ndw i dt h can b e p r ogrammed, t h is serves t h r e e purposes: 1 . s t a r t- u p ti m e o p ti m i s a ti o n , s t a r t- u p i s f a s t e r f o r h i g h e r s y n t h e s i z e r lo o p b a n d w i d t h s 2. tx s p ec tr um op t i mi s a t i o n , phase- noi s e a t 3 0 0 kh z t o 1 m h z d i st a n c e f r om th e carri e r impro v es wi th lower synt hesiz e r loop bandwid t hs 3 . a d a p ta ti o n o f th e b a n d w i d t h to t h e d a ta - r a t e . f o r tr a n s m i s s i o n o f f s k a n d m s k i t i s req u i r ed t h a t th e sy n t h e s i zer band wi d t h m u st be in the ord e r of t h e da t a - r a t e. versi o n 1. 3 datasheet a x 5031
circui t d e scr i pt ion 19 vc o an on-chip v c o conv e r ts t h e co nt ro l v o lt ag e gene rate d by the charge pu mp and l o op filt e r int o an output freque ncy. the fre q ue ncy can be programmed in 1 hz steps in the freq or freqb registers. to chose freqb sett i n g ra t h er than freq , t h e bi t fr eq s e l i n regi s t er pllloop mus t be se t . f o r opera t i o n i n the 43 3 m h z band , t h e ba nds e l bi t i n th e pllloop register must be programmed. vc o au t o - r an gi ng the a x 50 31 has an in teg r a t ed a u t o -r anging func t i on, which allo ws t o set the corr ec t v c o range for spe c ific fre q uency ge ne rat i on su bsyst e m set t i n gs aut o mat i call y. t y pical l y i t has t o be e x e c uted afte r powe r-u p . the funct i on is ini t iat e d by set t i n g t h e rng_ start bi t in t h e pl l r anging regi ster. the bi t i s r e a d abl e and a 0 i n d i ca t e s the end of t h e rangi n g pr ocess. the r n g e rr bi t i n d i ca te s t h e correc t exec u t i o n o f t h e a u t o - r a n gi ng. l o o p fi lt er an d ch ar ge pump the ax 50 3 1 int e rnal l oop fil t e r configu r at ion t o g e the r wi t h t h e charge pu mp cu rrent set s t h e synt he size r l oop band wid t h. the l oop-filt e r has three configu r at i o ns that can be programmed v i a t h e register bi t s fl t[ 1: 0] i n regis t er pl ll oop , t h e charg e pump c u rrent ca n be progra mmed usin g regis t er bits pll c p i [ 1 : 0 ] also in regis t er pllloop . s y nt he s i z e r band wi d t hs are t y pi cal l y 50 - 50 0 khz d e pend i n g on the pllloop sett i n gs , for det a ils see t h e sec t i o n 4. 3: a c charac t e ri s t i c s. reg i s t ers register bits purpose fr eq se l s w i t c h es b e t w een carri er frequ e nci e s defin e d by freq and fr eqb . u sing t h is fe a t ure all o w s t o av oi d g l it che s in the p ll ou tp u t f r eq uency caus e d b y s e ri al l y chan gi ng the 4 b y tes r e q u i r ed to s e t a carri er f r eq ue ncy . fl t[ 1 : 0 ] sy nthes i z er l o op f i l t er b a n d w i d th, r e co m m e nd ed us ag e i s to i n creas e th e b a nd w i d t h for faste r sett l i ng t i me, band w i dt h incre a se s of factor 2 and 5 are possibl e . p llcp i [2 :0 ] sy nthesizer c h a r ge pump current, r e c o mmend ed us ag e i s to decr eas e th e b a nd w i d t h ( a nd improv e the phas e - nois e) for l o w da ta-rate t r ansmissions. pl ll oop ba n d sel sw i t che s b e tw ee n 868 mh z / 915 mhz and 433 mhz bands freq programmin g o f t h e carri er frequency fr eq b prog ramming of t h e 2 nd carrier fre q uency, s w i t ch t o t h is carri er fre q uency by sett ing bi t fr eq se l= 1 . pl l r a n gi n g init iate v c o au t o -rang i ng and che c k re sul t s versi o n 1. 3 datasheet a x 5031
circui t d e scr i pt ion 20 5. 6. rf ou tpu t s tage ( antp/ a n tn) the a x 50 31 u s e s ful l y diffe rent ial ante nna pins. the pa d r i v es the si gn al gen e ra te d by t h e f r eq ue ncy gen e ra t i on s u bsy s te m o u t t o th e diffe re nt ial ante nna te rminal s. the output powe r of the pa is programmed v i a bi t s txrn g[3 : 0 ] i n t h e r e gi s t er txpwr . ou tpu t po w e r as we l l a s h a rmoni c co n t en t wi ll de pend on th e ex ter n a l i m ped a nc e se en by t h e pa, rec o mm end a t i ons ar e gi ven i n th e s e c t i o n 7: a ppli c a t i o n informat ion. 5. 7 . encod e r the en cod e r i s loca ted be tw e e n t h e fra m i n g u n i t and t h e m o d u la t o r. it ca n o p t i onal ly t r ansform t h e bi t - st re am in t h e foll owi n g ways: ? i t c a n inv e rt t h e b i t st re am . ? it can pe rform diffe re nt ial e n coding. this me ans t h at a ze ro is t r ansmi tte d as no chang e in the l e v e l , and a one is transmi t t e d as a chang e in t h e leve l . diffe re nt i a l encod i ng i s us ef u l f o r psk, becau s e ps k t r an smi ssi ons c a n be r e cei v ed ei ther a s t r ans m i tted or i n ver t ed, d u e t o t h e unc e r t ai n t y of the i n i t i a l pha s e . di ff eren t i a l e n coding / de coding remo v e s this unce rtaint y. ? it can p e rf orm manch e s t er enco ding. manches t er enc o ding ensur e s tha t th e m o d u la ti o n h a s n o d c c o n t e n t a n d e n o u g h tr a n s i ti o n s ( c h a n g e s f r o m 0 t o 1 a n d f r o m 1 to 0 ) f o r t h e d e m o d u la to r b i t t i m i n g r e c o v e r y to f u n c ti o n c o r r e c t ly , b u t d o e s s o a t a doubling of the da t a ra te. ? it c a n perfo r m spec t r al shaping. spec tral sha p ing re mo ves d c co n t en t of the bi t s t r e a m , e n s u r e s tr a n s i ti o n s f o r th e d e m o d u l a to r b i t ti m i n g r e c o ve r y , a n d m a k e s s u r e t h a t t h e tr a n s m i t t e d s p e c tr u m d o e s n o t h a ve discrete lin e s even if th e t r an smi t ted dat a is cyclic. i t do e s so without adding a d d i ti o n a l b i t s , i. e . w i th o u t c h a n g i n g th e da t a ra te. s p ectral s h a p ing uses a self synchronizing fe e d back shif t re giste r . the encoder is programmed using the register encoding , det a ils and re comme nd at ions on usag e are gi ve n i n t h e ax 503 1 programming manua l . versi o n 1. 3 datasheet a x 5031
circui t d e scr i pt ion 21 5. 8. fra m ing a n d fi fo m o s t r a d i o s y s t e m s to d a y g r o u p da ta i n to p a ckets. the framing u n i t is responsible for con v er t i ng thes e pa ck e t s i n t o a bi t - s t ream sui t ab l e f o r the mo d u la tor. the framing u n i t su pport s fou r diffe re nt mod e s: ? hdlc ? raw ? 80 2. 15. 4 comp li an t the micro-cont roll e r co mmu n icat es wi t h t h e framing u n i t t h rou g h a 32 lev e l 10 bi t fifo. the fi fo de co uple s micro-cont roll e r t i mi ng from th e radio ( m od ul ator) t i ming. the bo tt o m 8 bi ts of the f i fo con t ai n tran smi t d a ta. the top 2 bi t are us ed t o con v ey m e ta i n f o rma t i o n i n hdl c and 80 2. 15. 4 mod e s. they are un us ed i n raw mo de . the met a information consist s of packe t be gin / e n d informat ion and the result of cr c chec ks. the f i fo ca n b e wri tten in power- down mode. the f i fo c a n be oper a t ed i n po ll ed or i n t e rr up t d r i v en mod e s. in po ll ed mod e , t h e mi cro- cont roller must periodically read the fi fo sta t u s r e g i s t e r o r th e f i f o c o u n t r e g i s t e r to d e termi n e w h e t h e r t h e f i fo ne ed s s e r v i c i n g. in i n terr up t mod e em pt y, not em pt y, fu ll , not fu ll and programma bl e le ve l i n te rrup t s ar e pro v i d ed . the a x 50 31 signals interr upt s by asser t i n g ( d riv i ng h i gh) it s i r q line. the in ter r up t lin e is l e vel triggered, act i ve high. i n terr u p ts ar e ac know led g ed by remo v i n g th e ca us e f o r t h e int e rr upt , i. e . by emptyi n g o r f i lli ng th e f i fo. basi c f i fo s t a t u s ( e m p ty, fu ll, ov err u n, u n d e rrun, and t h e t o p two bi ts of th e t o p f i fo word ) are also pro v i d ed d u ri n g each sp i acces s on m i so whi l e th e mi cro- con t rol l er s h i f t s ou t th e re giste r addre ss on mosi . se e t h e spi int e rface se ction for de t a il s. this fe atu r e significant l y red u c e s th e nu mb er of sp i acc e ss es nec e s s ary . versi o n 1. 3 datasheet a x 5031
circui t d e scr i pt ion 22 hdlc m o de note : hdlc mode foll ows high-lev el dat a link cont rol ( h dlc , i s o 13239) pro t ocol. hdlc mode is the main framing mod e of t h e ax 50 31 . i n t h is mo de , t h e ax 50 3 1 performs a u to m a ti c p a c k e t d e li m i ti n g , a n d o p ti o n a l p a cket correc t ness check by inser t i n g and chec king a cyclic redundancy chec k ( c rc) field. the pa ck e t s t r u c t ur e i s gi ve n i n t h e f o llo wi ng t a b l e. flag address control infor m ation fcs (optional flag) 8 bit 8 bit 8 or 16 bit v a riabl e l e ngth, 0 or mor e bi t s in mul t ipl e s of 8 16 / 32 bit 8 bit hdlc pac k ets are deli mi ted wi t h flag seq u enc e s of con t en t 0x 7e. in ax 50 3 1 t h e m e ani n g of ad d r ess and con t rol i s us er d e f i n ed . the frame ch eck s e q u enc e ( f cs) can b e program m e d t o b e cr c-cc itt, crc-16 or cr c - 32. for det a ils on impleme n ting a hdlc commu n icat ion see t h e a x 50 31 programming manua l . ra w m o d e in raw mode, t h e a x 503 1 does no t perform any pack et deli mi t i ng or by te synchro n iza t ion. it simp ly seriali s es trans m i t bytes. this mode is ide a l for impl eme n t i ng legacy prot ocol s in sof t ware . 802 . 1 5 . 4 ( z i g bee) 80 2. 15. 4 us e s bi nary pha s e s h i f t key i n g ( p sk) wi t h 30 0 kbi t /s ( 8 68 m h z ban d ) or 600 kbi t /s ( 915 mhz band) on t h e radio. the usable bit ra te is only a 15 th o f t h e radio bit r a t e , however. a spre ading funct i on in the t r ansmi t te r e x pands t h e user bi t ra te by a fact or of 15, t o ma ke the t r a n sm is s i o n m o r e r o bu st . t h e des p rea d e r fu n c t i on o f t h e re ce iv e r u n does t h at . in 8 02. 1 5 . 4 mod e , t h e ax 503 1 framing u n i t pe rf orms t h e spre ading acc o rding t o t h e 802. 15. 4 spe c ificat io n. versi o n 1. 3 datasheet a x 5031
circui t d e scr i pt ion 23 5.9 . mo dul ato r d e p e n d i n g o n th e tr a n s m i t t e r s e t t i n g s th e m o d u la t o r genera tes v a riou s input s for t h e pa: modulation bit = 0 bit = 1 main lobe ban d width max. bitrate a s k pa off pa on b w = bi t r a t e 2000 kbit /s f s k / msk /gfsk ? f = -f deviat ion ? f = +f deviat ion b w = ( 1 +h) ? bi t r a t e 200 kbit /s psk ? = 0 0 ? = 180 0 b w = bi t r a t e 2000 kbit /s h = m o d u la t i o n i n d e x . i t i s th e r a ti o o f th e d e vi a t i o n c o m p a r e d to th e b i t- r a t e ; f de v i at i o n = 0. 5 ? h ? bi trate . ask = am pl i t u d e shift ke ying fsk = fre q ue ncy shift ke ying msk = minimum shift ke ying ; msk is a spe c ial case of fsk, whe r e h = 0 . 5 , and th eref ore f dev i at i o n = 0. 25 ? b i tra t e; the ad v a n t age of m s k o v er fsk i s t h a t i t can b e demod u la te d more robust ly. psk = phas e shif t keying oqpsk = offset qua d ratur e shif t keying. the a x 50 31 sup p or t s oqps k. however, un less compa t i b i l i t y t o an exi s t i ng sy s t em i s req u i r ed, m s k sho u ld b e pref err e d . 4- fsk = f o ur f r equ e nci e s are us ed t o t r a n smi t two bi ts si m u l t a n e o usly d u ri ng ea c h symbol modulation symb ol = 00 symb ol = 01 symb ol = 10 symb ol = 11 max. bitrate 4-f s k ? f = -3 ? f deviat ion ? f = -f deviat ion ? f = +f deviat ion ? f = +3 ? f deviat ion 400 kbit /s a ll mo d u la ti o n sch e m e s are bi nary . versi o n 1. 3 datasheet a x 5031
circui t d e scr i pt ion 24 5 . 10. pw rmode r e g i s t er the pwrmode regi s t er c o n t rols, whi c h par t s of th e chi p ar e opera t i n g. pw rm o d e register name description typical idd 0 0 0 0 p o w e rdo w n all digit a l and anal og func t i ons , ex cep t th e register fil e , ar e di s a b l ed. t h e c o re s u p p l y v o l t age i s re duc e d to cons erv e l e ak age pow e r. spi re g iste r s are s t ill acce ssib l e , bu t a t a s l ow e r spee d. fi f o acce ss is possib l e . 0. 25 a 0 1 0 0 v r ego n all digit a l and anal og func t i ons , ex cep t th e register fil e , ar e disabl e d . t h e core v o l t ag e, how e v e r is a t it s nominal v a l u e fo r ope r a t ion, a nd all sp i re g ist ers are acce ssibl e at the maximu m s p eed . 140 a 0101 st a n dby t h e crystal osci ll ator is po w e red on; the transmi tte r is off. 500 a 1 1 0 0 s y n t h t x th e sy nthesizer i s running o n t h e t r ansmi t frequ e ncy . the t r ans m itter is st ill off. t h is m o de is use d to let t h e synt he si ze r sett l e on the correc t frequ e n c y for t r a n smit. 10 m a 1 1 0 1 f u llt x sy nthesizer an d t r a n smitter ar e running. do no t s w i t ch in t o this mode b e fore the synt he siz e r has compl e t e l y s e tt l e d on the t r ansmit frequency ( i n synt h t x m o d e ), other w ise spuri o us spec t r al t r a n smissions w i l l occur. 11 - 45 m a a t y pical pwrmode sequence for a t r an sm it se ss ion : step pw rm o d e remarks 1 p o w e rdo w n 2 s t a n dby th e sett l i ng t i m e is domina ted by t h e cry s t a l used , t y pical v a lue 3ms. 3 s y n t h t x t h e synthe size r sett l i ng t i m e is 5 ? 50 s de pe nding on s e tt ing s , se e sect ion a c charac teris t ics 4 f u llt x data t r a n s m i s s i o n 6 p o w e rdo w n versi o n 1. 3 datasheet a x 5031
circui t d e scr i pt ion 25 5.1 1 . seri al pe ri ph er al inte r f a c e ( s pi) the ax 503 1 can be programmed v i a a four wir e seri al inter f ace ac cordin g spi u s ing t h e pins clk, mosi , mi so a n d sel. registers for sett ing up t h e ax 50 3 1 are program m ed v i a th e seri a l pe riphe r al inte rface in all dev i ce mo de s. w h e n t h e inte rface signal se l is pu lle d l o w, a 1 6 bit configu r at ion dat a st re am is e x pe ct e d on t h e input sig n al pin mosi, which is in terpreted a s d0... d7 , a0... a6 , r_n/ w . da t a read fr om t h e inter f ace appea r s on mi so. figure 5 sho w s a wri t e/r e ad acc e ss t o the inter f a c e . t h e d a t a s t r e a m i s b u i l t o f a n a d d r e s s byte incl u d i n g re ad/wri t e informat i o n and a da ta b y t e . de p e n d i n g o n th e r _ n / w bi t a n d address bi ts a[6.. 0 ], dat a d[7.. 0 ] can be wri t ten v i a mosi or read a t t h e pi n mi s o . r_n/ w = 0 me ans r e ad mode, r_n/ w = 1 mean s wri t e mod e . the r e ad sequence star ts wi th 7 bi ts of st a t us informat ion s[6 ..0 ] f o l l o we d by 8 dat a bi ts. the sta t us bits contain th e fol l o wing informat ion: s6 s5 s4 s3 s2 s1 s0 p ll lo ck fi fo o v er fi fo u n d e r fi fo f u ll fi fo emp t y fi fo st a t ( 1 ) fi fo st a t ( 0 ) spi t i ming ts h r/ w ss sc k mos i mi s o a6 a5 a4 a 3 a2 a1 d7 a 0 d6 d5 d4 d0 d1 d2 d3 d7 d6 d5 d4 d3 d 2 d1 d0 s6 s5 s4 s 3 s2 s1 s0 tssd tc o ts s t ck tch t cl th ts ts sz figure 5 serial p e ripheral interfa ce timing versi o n 1. 3 datasheet a x 5031
register bank descript io n 26 6. regi s te r b a nk d e scrip t io n thi s sec t i o n d e scri b e s t h e bi t s of t h e regi s t er b a nk i n d e t a i l . the regi s t ers are gro u p e d by f u n c ti o n a l b l o c k to f a c i li t a te p r o g r a m m i n g . no ch ecks are mad e wh e t h e r the programm ed combi n a t i o n of bi t s mak e s s e ns e! bi t 0 i s always the l s b. note w h ole registers or register bi t s marked as r e se r v ed sho u ld b e k e p t a t t h ei r d e f a ul t v a l u es. note a ll ad d r ess e s no t d o cum e n t ed her e m u s t n o t be accesse d , ne it he r in re ading nor in writ ing. versi o n 1. 3 datasheet a x 5031
register bank descript io n 27 6. 1 . cont rol regist er map addr name dir reset bit description 7 6 5 4 3 2 1 0 revision & interf ace probing 0 re v i s i o n r 00100001 si l i con r e v ( 7 : 0 ) s i l i c o n re v ision 1 sc r a tc h rw 11000101 s c r a t c h ( 7: 0) s c r a t c h r e g i s t e r operating mod e 2 pw rm o d e rw 011-0000 rst r e f e n x o e n - p w rmod e ( 3 : 0 ) pow e r mode crystal oscillator, part 1 3 xt al o s c rw ----0010 - - - - x t a l oscg m ( 3 : 0) gm of cry s t a l oscill at or fifo, part 1 4 fif o ct rl rw ------11 fi fo st a t ( 1 :0 ) fi fo o v er fi fo u n d e r fi fo f u ll fi fo emp t y fi fo cmd ( 1 : 0 ) fi fo control 5 fif o d a t a rw -------- fi fo da t a ( 7 :0 ) f i fo d a t a i n terrupt control 6 ir qm a s k rw -0000000 - i r q m as k( 6: 0) ir q m a s k 7 ir qr eq u e s t r -------- - i r q r e q ue s t ( 6 : 0 ) i r q r e q u es t i n terf ace & p i n control 0c pin c fg 1 rw 00101000 - i r qz - sysc lk ( 3 : 0 ) pin configura t i o n 1 0d pin c fg 2 rw 00000000 - i r qe - - i r q i - pin configura t i o n 2 0e pin c fg 3 rw 0------- reserv ed - - sysc lkr - i r qr - pin configura t i o n 3 0f ir qi n v er s i o n rw -0000000 - i r qi n v e r s i o n (6 :0 ) i r q i n v e r s i o n modulation & fr aming 10 modul a t i o n rw -0000010 - m o d u la t i on ( 6 :0 ) modul a t i o n 11 en codin g rw ---00010 - - - en c nosy nc en c ma nch en c scra m en c di ff en c i n v enco der / d e co der s e tt i n gs versi o n 1. 3 datasheet a x 5031
register bank descript io n 28 12 fr am ing rw -0000000 - h s u p p c r c m o d e( 1: 0) f r mm o d e( 2: 0) - f r a m i n g s e t t i n g s 14 crc i nit 3 rw 11111111 crci n i t( 31 : 2 4 ) crc i n it ia l i zat i o n da t a or pre a mbl e 15 crc i nit 2 rw 11111111 crci n i t( 23 : 1 6 ) crc i n it ia l i zat i o n da t a or pre a mbl e 16 crc i nit 1 rw 11111111 crci n i t( 15 : 8 ) crc i n it ia l i zat i o n da t a or pre a mbl e 17 crc i nit 0 rw 11111111 crci n i t( 7 : 0 ) crc i n it ia l i zat i o n da t a or pre a mbl e voltage regula tor 1b vr eg r -------- - - - - ssds ssreg sds sreg vol t a g e r e gul a t o r s t a t us synthesizer 1c fr eq b 3 rw 00111001 fr eq b ( 3 1 :2 4 ) 2 nd sy nth e s i z er f r eq ue ncy 1d fr eq b 2 rw 00110100 fr eq b ( 2 3 :1 6 ) 2 nd sy nth e s i z er f r eq ue ncy 1e fr eq b 1 rw 11001100 fr eq b ( 1 5 :8 ) 2 nd sy nth e s i z er f r eq ue ncy 1f fr eq b 0 rw 11001101 f r e q b( 7: 0) 2 nd sy nth e s i z er f r eq ue ncy 20 fr eq 3 rw 00111001 freq ( 3 1 : 24 ) s y n t h e s i z e r freq uency 21 fr eq 2 rw 00110100 freq ( 2 3 : 16 ) s y n t h e s i z e r freq uency 22 fr eq 1 rw 11001100 freq ( 1 5 : 8 ) s y n t h e s i z e r freq uency 23 fr eq 0 rw 11001101 freq ( 7 : 0 ) s y n t h e s i z e r freq uency 25 fskde v 2 rw 00000010 fsk d e v ( 2 3 : 1 6 ) f s k fr eq u e ncy dev i ati o n 26 fskde v 1 rw 01100110 fsk d e v ( 1 5 : 8 ) f s k fr eq u e ncy dev i ati o n 27 fskde v 0 rw 01100110 fsk d e v ( 7 :0 ) f s k fr eq u e ncy dev i ati o n 2c p lllo o p rw 00011101 fr eq se l res e rv ed ba ndse l p llcp i ( 2 :0 ) fl t ( 1 : 0 ) sy nthes i z er loo p fi l t er s e tti n gs 2d p l l r an g i ng rw 00001000 s t i c k y lo ck p ll lo ck r n ger r r n g s t a r t vco r ( 3 :0 ) sy nthes i z er vc o a u to-r a n gi n g transmitter 30 txpwr rw ----1000 ? ? ? ? t x r n g ( 3 : 0 ) t r ansmi t po w e r 31 txr a t e hi rw 00001001 txr a te ( 2 3 : 1 6 ) t r a n s m i t t e r bi tra t e versi o n 1. 3 datasheet a x 5031
register bank descript io n 29 32 txr a t e m i d rw 10011001 txr a te ( 1 5 : 8 ) t r a n s m i t t e r bi tra t e 33 txr a t e lo rw 10011010 txr a te ( 7 :0 ) t r a n s m i t t e r bi tra t e 34 modmisc rw ??????11 ? ? ? ? ? ? re se rv e d p ttlck ga t e misc rf f l ag s fifo, part 2 35 fif o co u n t r --000000 ? ? fi fo co un t ( 5 : 0 ) fi fo fil l s t a t e 36 fi fothr esh rw --000000 ? ? fi fo t h r e sh ( 5 :0 ) fi fo t h r e s h ol d 37 fif o co nt rol 2 rw 0-----00 cl e a r ? ? ? ? ? st opone r r ( 1 : 0 ) a ddit i onal f i f o cont rol crystal oscillator, part 2 4f xt al c a p rw --000000 ? ? xt al c a p( 5: 0) c r y s ta l o s c i l l a t o r tu n i n g capacitanc e 4-fs k c o n t r o l 50 fou r f s k rw -------0 ? ? ? ? ? ? f o u r fs ken a 4-f s k cont rol versi o n 1. 3 datasheet a x 5031
appl icat ion informat ion 30 7. appl ic at i o n i n fo rm at ion 7. 1 . typi cal a p pli c ation diagram sysc lk sel v d d an t p an t n v d d vreg vdd cl k16p cl k16n mosi irq vdd_i o a x5031 an t e n n a to/from micr o-control l er miso clk 1 f from powe r su pply vreg g n d figure 6 t y pical application dia g ram it is ma nda t ory t o add 1 f ( l ow esr) be tw ee n v r eg a n d g n d. decoupling capaci t o rs are no t a l l drawn. it is re comme n d e d t o add 1 0 0 nf de co u p l i ng capaci t o r for every v dd and v dd_i o pin. i n order t o re du ce noise on t h e ant e nna input s i t is recom m e nd ed t o ad d 2 7 pf on th e v d d pi ns close t o th e an t e nn a i n terf ace. versi o n 1. 3 datasheet a x 5031
appl icat ion informat ion 31 7 . 2. a n ten n a i n te r f a c e c i r c u i t r y a small a n tenn a can b e direc t ly c o nnec t ed to the ax 503 1 an tp and an tn pins wi t h an opt i onal transl ation network. the network mu s t pro v ide dc power to the pa. a biasing t o v r eg is necessary. be side biasing and impe dance mat c hing, t h e proposed network also pro v ides low pa ss fil te ring t o l i mi t spu r iou s e m ission. s i ng le -e nded a n t e nna i n terf ace c1 c3 c6 l4 50 ? si n g l e - ende d equ ipm ent or ante n n a ic an ten na pins vreg vreg l3 l2 l1 c2 l5 c4 c5 l6 ca cb lb figure 7 structure of the ant e nn a interface to 50 ? single-ende d equipment or antenna frequency band l1 =l2 [nh ] c1 [pf] l3 =l4 [nh ] c2 [pf] c3 =c5 [pf] l5 =l6 [nh ] lb [nh ] ca =cb [pf] c4 =c6 [pf] 868 / 915 mhz 33 2. 2 12 2. 2 1. 8 18 6. 2 8. 2 150 4 3 3 mhz 3 9 3 3 3 3 . 3 3. 3 3 9 1 2 1 8 1 5 0 7. 3. v o ltage r e gula t o r the ax 50 3 1 has an integrated v o ltage regula tor wh ich gene rates a st able suppl y v o lt ag e v r eg f r om the v o l t age appli e d a t v dd_ io. u s e v r eg t o su p p ly al l the v dd supp ly pi ns. versi o n 1. 3 datasheet a x 5031
q f n2 0 pa ck age inf o rma t i o n datasheet a x 5031 32 8. qfn20 package infor m ation 8. 1 . package out l ine q f n20 axsem ax5031-1 yyw wxx notes 12. jedec ref mo-220 13. all dimensions are in millimet ers 14. pin 1 is ident if ied by cham f e r on corner of exposed die pad. 15. dat u m c and t he seat in g plane are def ined by t he f l at surf ace o f t he met a llised t e rminal 16. dimension ?e? represent s t he t e rminal pit c h 17. dimension b appli e s t o met a llised t e rminal and is measured 0. 25 t o 0. 30mm f r om t e rminal t i p. 18. dimension l1 represent s t e rminal pull back f r o m package edge. w here t e rminal pull back esist s , only upper half of lead is visible on package edge due t o h a lf et ching of leadf rame. 19. package surf ace shall be mat t e f i nish, ra 1. 6-2.2 20. package warp shall be 0. 050 maximum 21. leadf rame mat e rial is c opper a194 22. coplanarit y appl ies t o the exposed pad as well as t he t e rminal 23. yyww x x is t he packa ging lot code versi o n 1. 3
q f n2 0 pa ck age inf o rma t i o n 33 8. 2 . qfn soldering prof ile profile feature pb-free proc ess av e r ag e ramp -u p ra t e 3c/sec max. p r eh ea t p r e h ea t t e m p e r at ur e m i n t sm i n 150c t e m p e r at ur e ma x t sm a x 200c ti m e (t sm i n to t sm a x ) t s 60 ? 180 se c t i me 25c t o peak t e mp e r a t u r e t 25 t o peak 8 min max. re fl ow phas e liquidus t e mperat u r e t l 217c t i m e ov er li q u i d us t e m p era t ur e t l 60 ? 150 se c peak t e mp era t ure t p 260c t i me w i t h in 5c of ac t ual peak t e m p e r at ur e t p 20 ? 40 se c cool ing phase ramp-do w n ra te 6c/sec max. not e s : a l l t e m p era t ures refe r t o t he t o p side of t h e pa ckage, m e asured on t he pack age b o dy surface. time p r e h e a t r e f l o w c o o l i n g t p t l t sma x t sm i n t p 25 c t s t l t 25 t o peak temperature versi o n 1. 3 datasheet a x 5031
q f n2 0 pa ck age inf o rma t i o n 34 8. 3 . qfn recommended pad layout 1. pcb land an d solder mas k ing recomm enda t i ons are sho w n in figure 9. a = c l e a r a nc e f r o m pc b t h er m a l pad t o s o ld er m a s k o p e n i n g , 0. 0635 mm m i n i m u m b = cl ea r a n c e f r om ed g e o f p c b th e r m a l pa d to p c b l a n d , 0 . 2 m m mi ni m u m c = cl ea ra n c e f r o m p c b l a n d e d g e t o s o ld er m a s k o p e n in g to be as t i g h t a s p o s s ib le t o en s u r e t h at s o m e s o ld er m a s k r e m a in s bet w e e n pc b pads d = pc b lan d le n g t h = q f n s o ld er p a d le n g t h + 0 . 1 m m e = pc b l a nd w i dt h = q f n so l d e r p a d wi dt h + 0. 1 mm figure 9 : p c b la nd and so lder mask reco mme ndations 2. ther mal vi as shou ld b e us ed on the pcb th erm a l pad ( m i d d l e grou nd pad ) t o i m p r ove th erma l con d uc t i v i t y f r om t h e d e v i c e t o a copp er ground pl ane are a on t h e re ver s e si d e of t h e pri n t e d ci rcui t b o ard . the num b er of v i as d e p e nd s on t h e pa ckage th er mal req u i r em en t s , as d e ter m i n ed by t h er mal si m u la ti on or ac t u a l tes t i n g. 3. incre a si ng the n u mb er of v i as thro u g h t h e pri n ted ci rcui t b o ard wi ll i m pro v e th e th erma l c o n d u c ti v i ty to th e r e v e r s e s i d e g r o u n d p l a n e a n d e x t e r n a l h e a t s i n k . i n g e n e r a l, a d d i n g more m e t a l t h roug h th e p c board und e r the i c wi l l i m prove o p era t i o nal hea t t r a n sf er, but will requ i r e care f u l attent ion t o unifo rm hea t i n g of t h e bo ard during assembly. 8. 4. a ssembly proces s st en ci l desi gn & solder paste appli c ation 1. s t ai nl es s s t e e l s t e n ci ls ar e reco m m e n d e d f o r sol d er pas t e a ppli c a t i o n. 2. a sten ci l thi c kne ss of 0. 12 5 ? 0. 150 m m ( 5 ? 6 mi ls) i s recom m e n d e d f o r scree n i n g. 3. for t h e pc b t h erma l pa d, sold er pas t e sho u ld be pri n ted on t h e p c b by d e si gni n g a s t enci l wi t h an array of smal l e r ope n i n gs t h a t s u m t o 50% of th e q f n ex posed pad area. solder paste should be a ppli e d through an arra y of squar e s ( o r circles) a s show n in fig u re 10. 4. the a p er tur e op eni n g f o r th e si gna l pad s sho u l d be be tw e e n 5 0 - 80% of the q f n p a d area as sho w n in figur e 11. 5. op t i ona lly , for be tter sol d er pas t e r e lea s e, t h e a p er tur e wa l l s sho u ld b e t r ap ezoi d a l and the corner s rounded. versi o n 1. 3 datasheet a x 5031
q f n2 0 pa ck age inf o rma t i o n 35 6. the f i n e pi t c h of the ic l e ad s re qui r e s accura te ali g nm en t o f the s t e n ci l and t h e pri n ted circu i t board. the stencil and printed circu i t as se mbl y sho u ld be al igned t o wi t h in + 1 mi l pri o r t o app l i c a t i o n of t h e sold er pas t e. 7 . n o -cle an flu x is re co mmende d since flu x f r o m u n d e rn e a th the th e r mal p a d w i ll b e diff icu l t to cle a n if wate r-sol u ble flu x is u s e d . figure 10 : solder paste applicat ion on ex p o sed pad minimum 50% coverage 62 % coverage maximum 80% coverage figure 11 : solder paste applicat ion on pins versi o n 1. 3 datasheet a x 5031
life su pport appl icat ions 36 9. l i fe su pport app l i c a t i o ns t h is p r o d u c t is n o t d e s i g n e d f o r u s e in l i f e s u pport appl i a nces, devi ces, or i n systems where m a l f un c t io n o f t h is p r o d u c t c a n r e as o n a b l y b e expected to res u l t i n pe rs o n al i n jury . axse m c u s t o m e r s us i n g o r s e l l in g t h is p r o d u c t f o r u s e in s u ch a p p l ic a t io n s do so a t t h e i r o w n r i s k a n d ag r e e t o f u l l y in d e m n if y a x s e m f o r a n y d a ma g e s r e s u l t in g f r o m s u c h im p r o p e r u s e o r s a l e . versi o n 1. 3 datasheet a x 5031
c o nt act i n for m at ion 37 10. c o nt a c t in for m at ion ax sem ag oskar-bider-s t rasse 1 ch- 8 60 0 d bend orf sw it z e r l a n d phon e +41 44 8 82 1 7 0 7 fax +41 44 8 82 1 7 0 9 e m ai l sale s@axsem.com www. axs e m . com for fu rt he r produ c t re lat e d or sal e s i n format ion ple a se v i si t ou r we bsi t e or cont act y o u r l o cal re present a t i v e . t h e s p ecif icat io ns in t his do cu m e nt are s u bject t o change a t a x s e m' s dis c r e t i o n . a x s e m as s u me s no res p o n s ibilit y f o r any claim s or d a m a g e s a r i s i n g out of t h e use of t h i s d o c u m e n t , or fr om t h e u s e o f pro d u c t s bas e d o n t his d o cu m e nt , inclu ding bu t no t limit ed t o c l aims o r da mages bas e d o n inf ringement o f pat e nt s , c o py right s o r o t her int ellect u a l pro p ert y right s . a x s e m make s no w a rran t ies , eit h er exp r es s e d o r implied w i t h res p ect t o t h e inf o r mat i o n and s p ecif ica t io ns co nt a ined in t his do cu ment . a x s e m do es no t s u ppo rt a n y applica t io ns i n co nne ct io n w i t h lif e s u ppo rt and co mmercia l aircraf t . p e rf o r mance c h aract eris t i cs lis t e d in t h i s do c u ment are es t i mat e s o nly and d o no t co n s t i t u t e a w a rra nt y or g u a r a n t ee of p r od uc t p e rf orm a n c e . th e co py ing , dis t ribu t i o n and u t iliz at io n o f t his do c u m e nt as w e ll as t h e co mmu nicat io n o f it s co nt ent s t o o t hers w i t h o u t expres s e d au t h o r iz at io n is pro hibit ed. o f f e nders w ill be held liable f o r t h e pay m ent of damages . all righ t s reserved . c o p y rig h t ? 2007 a x se m a g versi o n 1. 3 datasheet a x 5031

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